Analog IC Layout Interview Questions

1.  How do you choose the height of Standard cells?
2. What are the constraints you will follow while doing standard cells.
3. How you will take care of power in standard cells?
4.  what is the difference between higher and lower node technologies?
5. what is poly pitch?
6. CMOS and finfet difference?
7. Advantages and disadvantages? and why?
8. Fabrication of FinFet?
9. what are challenges did you face in lower node technologies?
10. what is meant by Fins?
11. How do you plan for device placement?
12. How you will identify Analog and Digital layout?
13. which one you will give more priority
14. Analog or digital layout? How do you separate in layout?
15.  how do you calculate metal width and length?
16.  what are the ways to reduce mental resistance?
17. what is meant by metal stag?
18. How do you choose power metal?
19. High-speed layout how you will reduce resistance?
20. what is mean by contact and via?
21. How many vias you will use and how it will help to reduce resistance.
22. what is mean resistance shielding?
23.  Draw the symbol of NMOS & PMOS Transistor? Explain each terminal and where it connects?
24. Explain the operation of the NMOS Transistor?
25. Transistor Second-Order Effects
26. What is Threshold voltage?
27. What is the hot-electron effect?
28. what is channel length modulation
29. what are subthreshold leakages
30. What is meant by Latch-up? What is the solution to solve latch-up issues? How you will take care while doing the layout?
31. What is mean by Guard ring? What are the types of Guard rings? How it will help to reduce latch-up?
32. What is Deep N-well guarding?
33. what is meant by antenna? what is the solution to reduce the antenna effect in the layout?
34. From where accumulated charges are coming?
35. Where is the discharge path?
36. How do jumper and diode will help?
37. No place to add diode and jumper what you will do?
38. Explain about shielding? Types of shielding? What are the signals you will do shielding and why?
39. Where you will connect shielded lines and why? Without shielding what will happen?
40. what is meant by cross-talk?
41. Describe the Electromigration effect? & ways to reduce Electromigration during layouts?
42. what is ESD? how you will fix ESD problems in the layout?
43. what is WPE, LOD & STI? Explain with diagram
44. What is matching? Types of matching and explain one by one? What will happen not doing matching?
45. how you can match resistor & capacitor layouts?
46. what are the advantages and disadvantages of Common centroid & interdigitated patterns?
47. how to improve the match of the current mirror, differential pairs
48. What are dummy Transistors
49. Describe DFM?
50. what is STD cells? How you will decide the height of STD cells?
51.  what is meant by Track?
52. What is meant by a pitch?
53. Draw the diagram of INV, NAND, and OR gates.

All the best!