Intel is currently hiring an Engineer for their company for various posts. This opportunity is open to students from the Electronics and Communication branch who are interested in applying for the Intel Recruitment 2023. If you meet the eligibility criteria and are interested in this role, you can read more details about the position and its responsibilities. This is an excellent opportunity for anyone looking to gain valuable experience in the field of Engineer. Apply now to join the Seagate team!

Intel Recruitment 2023

Organization Name Intel
Post Name SoC Design Engg – Intern / Graduate Intern /CAD Engineer
Salary up to ₹10 LPA*
Job Location Bengaluru
Batch 2023 and before batch
Official Website https://intel.com/

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Job Responsibilities for CAD Engineer:

  • Develops and applies computer aided design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical problems.
  • Assessing architecture and hardware limitations, plans technical projects in the design and development of CAD software.
  • Defines and selects new approaches and implementation of CAD software engineering applications and design specifications and parameters.
  • Develops routines and utility programs.
  • Prepares design specifications, analysis and recommendations for presentation and approval.
  • May specify materials, equipment and supplies required for completion of projects and may evaluate vendor capabilities to provide required products or services.

CAD Engineer Eligibility Criteria:

  • Master in Electronics/ Computer science Engineering

CAD Engineer Preferred skill:

  • Proficiency in SKILL/Python/TCL programming language
  • Exposure to C/C++/or other functional programming language
  • Experience in Virtuoso Layout design and SKILL programming is added advantage
  • Teamwork, communication (vertical and/or horizontal) and problem-solving skills
  • In depth knowledge in Data Structures, Algorithms and Optimizations
  • Good understanding in VLSI domain

Apply link CAD Engineer: Click here

Job Responsibilities for Graduate Intern:

  • Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGA’s, etc.) 
  • C/C++ and Python are the most useful languages for our work.
  • VLSI concepts -Power Management / Reset o Familiarity with FW (embedded uC) debug ARC or Extensa LX-series uC preferred
  • Knowledge of ARM PM concepts (e.g., P/Q-channel)
  • General clocking concepts (PLL’s, RO’s, etc.) o Ability to debug interactions between different microcontrollers o Understanding power delivery concepts, VR interactions, etc. –
  • Mesh / Coherency o Knowledge of coherence algorithm (MESI, MOESI, MESIF, etc.). o Experience with SoC fabrics (AXI, ACE or other AMBA protocols). o Understanding transaction flows through the system. – PCI Express (we can leverage this expertise for other IO’s, like CXL). o Familiarity with any generation of the PCI Express specification o Usage of 3rd party PCIe Analyzers very helpful (Tek, Lecroy, etc.) -Memory o Expertise in any DDR technology. o Usage of 3rd party DDR Analyzers very helpful (Tek, Lecroy, etc.)

Graduate Intern Eligibility Criteria:

  • Pursuing Master’s in Hardware Engineering or Electrical/Electronic Engineering or Computer Engineering or Computer Science

Graduate Intern Preferred skill:

  • Excellent Problem solving skills combined with good communication skills required to work in a high dynamic cross team and cross site environments.
  • Ability to learn fast.
  • Big Plus if you have any of the following knowledge:

Apply link Graduate Intern: Click here

Job Responsibilities for SoC Design Engg Intern:

  • Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation.
  • Performs Logic design for integration of cell libraries, functional units and subsystems into SoC full chip designs,
  • Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits.
  • Performs all aspects of the SoC design flow from highlevel design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing.
  • Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results.

SoC Design Engg Intern Eligibility Criteria:

  • ME/MTech 

SoC Design Engg Intern Preferred skill:

  • Strong written and verbal communication skills.

Apply link SoC Design Engg Intern: Click here

About Intel:

At Seagate, our mission is to give people peace of mind by protecting their digital lives. Since 1978, Seagate has been creating precision-engineered data storage technologies that deliver superior capacity, speed, safety, and performance. We help people harness and maximize the datasphere.